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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
November. 1999. Ver. 0.1
Prepared by
Dae-Young, Ahn
Mail: jesus9@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668 Specification Revision History Version 0.0 0.1 Original The contents of page 16, 17 and 18 have been modified Content Date Aug.1999 Nov.1999
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
CONTENTS
INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSIGNMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS........................................................................................................................................... 7 OPERATION DESCRIPTION .............................................................................................................................. 8 DISPLAY DATA TRANSFER............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15 RECOMMENDED OPERATION CONDITIONS ................................................................................................. 15 DC CHARACTERISTICS................................................................................................................................... 16 AC CHARACTERISTICS................................................................................................................................... 17 WAVEFORMS ................................................................................................................................................... 18 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 19
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0668 is a 384 channel output, TFT-LCD source driver for an 64 gray-scale LCD panel. Data input is based on digital input consisting of 6 bits by 6 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma-corrected. This device has an internal D/A (digital-to-analog) converter for each output and 10 (5-by-2) reference voltages. Because the output dynamic range is as large as 4.8 - 7.8 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray-scale voltages with different polarity can be output to the odd number output pins and the even output pins. S6C0668 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MHz at 2.7 V logic operation, single edge and it can be applied to the TFT-LCD panel of XGA to SXGA standard.
FEATURES
* * * * * * * * * * * * TFT active matrix LCD source driver LSI 64 gray-scale is possible through 10 (5-by-2) reference voltages and D/A converter Both dot inversion display and N-line inversion display are possible CMOS level input Compatible with gamma-correction Input data inversion function (DATPOL) Logic supply voltage: 2.7 - 3.6 V LCD driver supply voltage: 5.0 - 8.0 V Output dynamic range: 4.8 - 7.8 Vp-p Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 2.7 V operation) Output: 384 outputs TCP available
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
BLOCK DIAGRAM
Y384
Y383
Y382
Y003
BIAS
Output Buffer
TEST
POL VGMA1 VGMA10
10
D/A Converter
6
6
6
6
6
Y002 6 DIO1
6
CLK1
Data Latch
6
6
6
6
6
DATPOL D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 6 Data Control 6 6 6 6 6 36
Data Register
64bit Shift Register
CLK2
DIO2
SHL
Figure 1. S6C0668 Block Diagram
Y001
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001 Y002 Y003 Y004
DIO1 D00 D01 D02 D03 D04 D05 D10 D11 D12 D13 D14 D15 D20 D21 D22 D23 D24 D25 TEST DATPOL POL CLK1 CLK2 VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VSS2 VDD2 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 SHL VDD1 D30 D31 D32 D33 D34 D35 D40 D41 D42 D43 D44 D45 D50 D51 D52 D53 D54 D55 DIO2
S6C0668
Y381 Y382 Y383 Y384
Figure 2. S6C0668 Pin Assignments
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(Top View)
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
PIN DESCRIPTIONS
Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y384 D0<0:5> - D5<0:5> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs Display data input 2.7 - 3.6 V 5.0 - 8.0 V Ground (0 V) Ground (0 V) The D/A converted 64 gray-scale analog voltage is output. The display data is input with a width of 36 bits, gray-scale data (6 bits) by 6 dots (R,G,B) DX0: LSB, DX5: MSB Description
SHL
This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. Shift direction control input SHL = H: DIO1 input, Y1 Y384, DIO2 output SHL = L: DIO2 input, Y384 Y1, DIO1 output Start pulse input / output Start pulse input / output SHL = H: Used as the start pulse input pin SHL = L: Used as the start pulse output pin SHL = H: Used as the start pulse output pin SHL = L: Used as the start pulse input pin DATPOL = H: Display data is inverted DATPOL = L: Display data is not inverted Detects H or L at rising edge of every CLK2. POL = H: The reference voltage for odd number outputs are VGMA1 - VGMA5 and those for even number outputs are VGMA6 - VGMA10 POL = L: The reference voltage for odd number outputs are VGMA6 - VGMA10 and those for even number outputs are VGMA1 - VGMA5 Refer to the shift register's shift clock input. The display data is loaded to the data register at the rising edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the gray-scale data at falling edge. Input the gamma corrected power supplies from external source. VDD2 > VGMA1 > VGMA2 > ......... > VGMA9 > VGMA10 > VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. TEST = L: Normal operation mode TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15k)
DIO1 DIO2
DATPOL
Data inversion input
POL
Polarity input
CLK2
Shift clock input
CLK1
Latch input
VGMA1 - VGMA10 TEST
Gamma corrected power supplies
Test input
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the data transfer operation, so display data is valid on the next rising edge of CLK2. Once all the data of 384 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2). EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device. RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE The LCD drive output voltages are determined by the input data and 10 (5-by-2) gamma corrected power supplies (VGMA1 - VGMA10). Besides, to be able to deal with dot-line inversion when mounted on a single-side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 5-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 5 gamma corrected voltages of VGMA1 - VGMA5 and VGMA6 VGMA10.
SHL = H
OUTPUT DATA D00 - D05 Y1 Y2 First D10 - D15 D20 - D25 ...... D30 - D35 Y3 ...... Y382 Y383 Last D40 - D45 D50 - D55 Y384
SHL = L
OUTPUT DATA D00 - D05 Y1 Y2 Last D10 - D15 D20 - D25 ...... D30 - D35 Y3 ...... Y382 Y383 First D40 - D45 D50 - D55 Y384
Figure 3. Relationship between Shift Direction and Output Data
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
VDD2 VGMA1
VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9
VCOM
VGMA10 VSS2 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input data
Figure 4. Gamma Correction Curve
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R62, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Value 500 500 500 500 500 500 500 500 500 500 500 500 450 450 400 370 Name R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 330 330 330 320 300 280 270 260 250 240 230 220 210 200 190 180 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 Value 175 175 170 170 165 165 165 165 170 170 170 175 175 175 180 200 Name R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 Value 210 220 230 240 250 260 270 290 300 310 320 340 340 340 340
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
Table 2. Relationship between Input Data and Output Voltage Value Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 Output voltage VGMA1 VGMA1 + (VGMA2 - VGMA1) x 500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 1000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 1500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 2000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 2500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 3000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 3500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 4000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 4500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 5000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 5500 / 7670 VGMA1 + (VGMA2 - VGMA1) x 6000 / 7670 VGMA1 + (VGMA2 - VGMA1) x 6450 / 7670 VGMA1 + (VGMA2 - VGMA1) x 6900 / 7670 VGMA1 + (VGMA2 - VGMA1) x 7300 / 7670 VGMA2 VGMA2 + (VGMA3 - VGMA2) x 330 / 4140 VGMA2 + (VGMA3 - VGMA2) x 660 / 4140 VGMA2 + (VGMA3 - VGMA2) x 990 / 4140 VGMA2 + (VGMA3 - VGMA2) x 1310 / 4140 VGMA2 + (VGMA3 - VGMA2) x 1610 / 4140 VGMA2 + (VGMA3 - VGMA2) x 1890 / 4140 VGMA2 + (VGMA3 - VGMA2) x 2160 / 4140 VGMA2 + (VGMA3 - VGMA2) x 2420 / 4140 VGMA2 + (VGMA3 - VGMA2) x 2670 / 4140 VGMA2 + (VGMA3 - VGMA2) x 2910 / 4140 VGMA2 + (VGMA3 - VGMA2) x 3140 / 4140 VGMA2 + (VGMA3 - VGMA2) x 3360 / 4140 VGMA2 + (VGMA3 - VGMA2) x 3570 / 4140 VGMA2 + (VGMA3 - VGMA2) x 3770 / 4140 VGMA2 + (VGMA3 - VGMA2) x 3960 / 4140
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39 VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47 VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55 VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63 Output voltage VGMA3 VGMA3 + (VGMA4 - VGMA3) x 175 / 2765 VGMA3 + (VGMA4 - VGMA3) x 350 / 2765 VGMA3 + (VGMA4 - VGMA3) x 520 / 2765 VGMA3 + (VGMA4 - VGMA3) x 690 / 2765 VGMA3 + (VGMA4 - VGMA3) x 855 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1020 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1185 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1350 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1520 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1690 / 2765 VGMA3 + (VGMA4 - VGMA3) x 1860 / 2765 VGMA3 + (VGMA4 - VGMA3) x 2035 / 2765 VGMA3 + (VGMA4 - VGMA3) x 2210 / 2765 VGMA3 + (VGMA4 - VGMA3) x 2385 / 2765 VGMA3 + (VGMA4 - VGMA3) x 2565 / 2765 VGMA4 VGMA4 + (VGMA5 - VGMA4) x 210 / 4260 VGMA4 + (VGMA5 - VGMA4) x 430 / 4260 VGMA4 + (VGMA5 - VGMA4) x 660 / 4260 VGMA4 + (VGMA5 - VGMA4) x 900 / 4260 VGMA4 + (VGMA5 - VGMA4) x 1150 / 4260 VGMA4 + (VGMA5 - VGMA4) x 1410 / 4260 VGMA4 + (VGMA5 - VGMA4) x 1680 / 4260 VGMA4 + (VGMA5 - VGMA4) x 1970 / 4260 VGMA4 + (VGMA5 - VGMA4) x 2270 / 4260 VGMA4 + (VGMA5 - VGMA4) x 2580 / 4260 VGMA4 + (VGMA5 - VGMA4) x 2900 / 4260 VGMA4 + (VGMA5 - VGMA4) x 3240 / 4260 VGMA4 + (VGMA5 - VGMA4) x 3580 / 4260 VGMA4 + (VGMA5 - VGMA4) x 3920 / 4260 VGMA5
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 VL9 VL10 VL11 VL12 VL13 VL14 VL15 VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23 VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31 Output voltage VGMA10 VGMA10 + (VGMA9 - VGMA10) x 500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 1000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 1500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 2000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 2500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 3000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 3500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 4000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 4500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 5000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 5500 / 7670 VGMA10 + (VGMA9 - VGMA10) x 6000 / 7670 VGMA10 + (VGMA9 - VGMA10) x 6450 / 7670 VGMA10 + (VGMA9 - VGMA10) x 6900 / 7670 VGMA10 + (VGMA9 - VGMA10) x 7300 / 7670 VGMA9 VGMA9 + (VGMA8 - VGMA9) x 330 / 4140 VGMA9 + (VGMA8 - VGMA9) x 660 / 4140 VGMA9 + (VGMA8 - VGMA9) x 990 / 4140 VGMA9 + (VGMA8 - VGMA9) x 1310 / 4140 VGMA9 + (VGMA8 - VGMA9) x 1610 / 4140 VGMA9 + (VGMA8 - VGMA9) x 1890 / 4140 VGMA9 + (VGMA8 - VGMA9) x 2160 / 4140 VGMA9 + (VGMA8 - VGMA9) x 2420 / 4140 VGMA9 + (VGMA8 - VGMA9) x 2670 / 4140 VGMA9 + (VGMA8 - VGMA9) x 2910 / 4140 VGMA9 + (VGMA8 - VGMA9) x 3140 / 4140 VGMA9 + (VGMA8 - VGMA9) x 3360 / 4140 VGMA9 + (VGMA8 - VGMA9) x 3570 / 4140 VGMA9 + (VGMA8 - VGMA9) x 3770 / 4140 VGMA9 + (VGMA8 - VGMA9) x 3960 / 4140
NOTE: VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VSS2
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 G/S VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39 VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47 VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55 VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63 Output voltage VGMA8 VGMA8 + (VGMA7 - VGMA8) x 175 / 2765 VGMA8 + (VGMA7 - VGMA8) x 350 / 2765 VGMA8 + (VGMA7 - VGMA8) x 520 / 2765 VGMA8 + (VGMA7 - VGMA8) x 690 / 2765 VGMA8 + (VGMA7 - VGMA8) x 855 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1020 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1185 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1350 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1520 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1690 / 2765 VGMA8 + (VGMA7 - VGMA8) x 1860 / 2765 VGMA8 + (VGMA7 - VGMA8) x 2035 / 2765 VGMA8 + (VGMA7 - VGMA8) x 2210 / 2765 VGMA8 + (VGMA7 - VGMA8) x 2385 / 2765 VGMA8 + (VGMA7 - VGMA8) x 2565 / 2765 VGMA7 VGMA7 + (VGMA6 - VGMA7) x 210 / 4260 VGMA7 + (VGMA6 - VGMA7) x 430 / 4260 VGMA7 + (VGMA6 - VGMA7) x 660 / 4260 VGMA7 + (VGMA6 - VGMA7) x 900 / 4260 VGMA7 + (VGMA6 - VGMA7) x 1150 / 4260 VGMA7 + (VGMA6 - VGMA7) x 1410 / 4260 VGMA7 + (VGMA6 - VGMA7) x 1680 / 4260 VGMA7 + (VGMA6 - VGMA7) x 1970 / 4260 VGMA7 + (VGMA6 - VGMA7) x 2270 / 4260 VGMA7 + (VGMA6 - VGMA7) x 2580 / 4260 VGMA7 + (VGMA6 - VGMA7) x 2900 / 4260 VGMA7 + (VGMA6 - VGMA7) x 3240 / 4260 VGMA7 + (VGMA6 - VGMA7) x 3580 / 4260 VGMA7 + (VGMA6 - VGMA7) x 3920 / 4260 VGMA6
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6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Output voltage Operating power dissipation Operation temperature Storage temperature Symbol VDD1 VDD2 VGMA1 - 10 Others DIO1, 2 Y1 - Y384 Pd Top Tstg Ratings -0.3 to 5.5 -0.3 to 9.0 -0.3 to VDD2 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 200 (1) -20 to 75 -55 to 125 Unit V V V V mW C C
NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd CL* (VDD2)2 * fCLK1)
CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 - VGMA10 Turn off power order: VGMA1 - VGMA10 VDD2 control signal input VDD1
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency Output load capacitance Symbol VDD1 VDD2
(1)
Min. 2.7 5.0 0.5VDD2 VSS2 + 0.1 VSS2 + 0.1
Typ. 3.0 7.0 -
Max. 3.6 8.0 VDD2 - 0.1 0.5VDD2 VDD2 - 0.1 55 200
Unit V V V V V MHz pF / PIN
VGMA1 - VGMA5 VGMA6 - VGMA10 Vyo fmax CL
(1)
VDD1 = 2.7 V -
NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd CL* (VDD2)2 * fCLK1)
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S6C0668
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V) Parameter High level input voltage Low level input voltage Input leakage current High level output voltage Low level output voltage Resistor Symbol VIH VIL IL VOH VOL R0 - R62 IVOH Driver output current IVOL Output voltage deviation Output RMS voltage deviation Output voltage range Logic part dynamic current Driver part dynamic current VO DIO1 (DIO2), IO = -1.0 mA DIO1 (DIO2), IO = +1.0 mA Refer to Table 1. Resistor Strings VDD2 = 7.0 V, Vx = 2.5 V, Vyo = 6.5 V(1) VDD2 = 7.0 V, Vx = 4.5 V, Vyo = 0.5 V(1) VSS2 + 0.1 V - VDD2 - 1.4 V VDD2 - 1.4 V - VDD2 - 0.1 V VSS2 + 1.4 V - VDD2 - 1.4 V dVrms Vyo IDD1 IDD2
(2)
Condition SHL, CLK2, D00 - D55, CLK1, DATPOL, POL, DIO1 (DIO2)
Min. 0.6VDD1 0 -1 VDD1 - 0.5 Rn x 0.7 0.5 VSS2 + 0.1 -
Typ. -1.0 1.0 10 20 5 20 4.0 4.0
Max. VDD1 0.3VDD1 1 0.5 Rn x 1.3 -0.5 20 10 30 VDD2 - 0.1 5.5
Unit V A V mA mA
mV
VSS2 + 0.1 V - VSS2 + 1.4 V VDD2 - 1.4 V - VDD2 - 0.1 V Input data: 00H to 3FH VDD1 = 3.0 V (3) VDD1 = 3.0 V, VDD2 = 7.0 V
(3)(4)(5)
V
mA 10.0
NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y384. Vx is the voltage applied to analog output pins Y1 to Y384. 2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray-scale. 3. CLK1 period is defined to be 20 s at fCLK2 = 33 MHz, data pattern = 101010(checkerboard pattern), Ta = 25 C. 4. The current consumption per a driver when XGA single-sided mounting (8 drivers) is connected in cascade 5. No Load
16
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0668
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time DATPOL-CLK2 setup time DATPOL-CLK2 hold time Start pulse delay time CLK1 setup time Driver output delay time1 Driver output delay time2 CLK1 pulse high period Data invalid period Last data timing CLK1 - CLK2 time POL - CLK1 time Symbol PWCLK PWCLK (L) PWCLK (H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP4 tHOLD4 tPLH1 tSETUP3 tPHL1 tPHL2 PWCLK1 tINV tLDT tCLK1 - CLK2 tPOL -CLK1 Condition (1) (1) (1) (1)
Min. 18 5 5 4/6 0/2 4/6 0/2 4/6 0/2 2 0.2 1 6 5
Typ. 1 -
Max. 12 5 10 2 -
Unit
ns
(1)
(1)
CL = 20pF (2), (4) (3), (4)
CLK2 period s
DIO1 (2) CLK2 CLK1 CLK2 POLor CLK1
CLK2 period ns ns
NOTES: 1. Input condition (VIH = 0.6VDD1, VIL = 0.3VDD1 / VIH = 0.5VDD1, VIL = 0.5VDD1) 2. The value is specified when the drive voltage value reaches the target output voltage level of 90% 3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. 4. Yout Load Condition
10k YOUT
20k
20k
30pF VCOM = 0.5VDD2
30pF
30pF
Figure 5. Yout Load Condition
17
18
PWCLK tINV 1st tHOLD1 VIH VIL LAST-1 LAST PWCLK (L) PWCLK (H)
S6C0668
CLK2
WAVEFORMS
DXX
INVALID DATA tSETUP4 tHOLD4
tSETUP1 1st DATA
DATPOL
tSETUP2 tHOLD2
DIO1 input (DIO2 input)
tPLH1
DIO2 output (DIO1 output)
tSETUP3 PWCLK1 tPHL1
CLK1
Target output voltage 90%
Y(1:384) tPHL2 HI-Z
Figure 6. Waveforms
tLDT tCLK1 - CLK2 0.5VDD1 LAST DATA tPOL - CLK1
Target output voltage
CLK2
CLK1
DXX
INVALID DATA
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
POL
CLK2
DIO1 input (DIO2 input)
0.5VDD1 1CLK2 3CLK2 (Min.) tLDT Nth DATA INVALID DATA blanking time = Min. 5CLK2 First data in the next line 1st DATA 2nd DATA
CLK1
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
DXX
N-1th DATA
Last data
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 7. Waveforms
HI-Z HI-Z HI-Z VGMA6 - VGMA10 VGMA1 - VGMA5 VGMA1 - VGMA5 VGMA6 - VGMA10
CLK1
POL
HI-Z
Y2N-1: odd number output
VGMA6 - VGMA10
Y2N: even number output
VGMA1 - VGMA5
S6C0668
19

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